34.4: High electrical stability nanocrystalline silicon BCE TFTs for outdoor display application on large glass substrates. (26th August 2021)

• Record Type: Journal Article
• Authors: Mai, Jiaying; Jiang, Zhixiong; Xu, Hongyuan; Zhu, Maoxia; Hu, Cong; Wang, Xu; Son, Woosung
• Is Part Of: Digest of technical papers. Volume 52(2021)Supplement 2
• Page Start: 458
• Page End: 461
• Publication Date: 2021-08-26
• Subjects: nanocrystalline-Si -- thin-film transistors -- electrical stability -- bottom gate; Information display systems -- Congresses; 621.3815422
• DOI: 10.1002/sdtp.15160
• Languages: English
• ISSNs: 0097-966X

Abstract

Abstract : We have fabricated high stability nanocrystalline silicon (NanoSi) on large glass substrate and investigated the effects of silane content ratio (SC), power, space and pressure on NanoSi thin‐film growth, deposition rate and its electrical characteristics on bottom‐gate back‐channel etch TFTs using 4 mask process. The single film results show that the key factors affecting the deposition rate are power and silane content and a suitable thickness is benifit for high mobility TFT manufacture. Multiple sets of data show that the main impact factor for electrical charecteristics of NanoSi TFTs is SC and pressure. Through the analysis of bias stress data, we can find that the electrical stability of NanoSi TFTs is better than that of a‐Si:H TFTs with lower Vth shift about 2.22 V of PBTIS and ‐1.29 V of NBTIS. It is because the defect state of NanoSi is produced by charge trapping and is negligible.