A digital background calibration scheme for non-linearity of SAR ADC using back-propagation algorithm. (August 2021)

• Record Type: Journal Article
• Authors: Lu, Hao-wei; Yu, Xiao-Peng; Wang, Si-Qi; Liu, Yu-Yan; Huang, Zhen-Yan; Lu, Zheng-Hao; Yeo, Kiat-Seng; Chen, Jer-Ming
• Is Part Of: Microelectronics journal. Volume 114(2021)
• Publication Date: 2021-08
• Subjects: Successive approximation register(SAR) -- Analog-to-digital converter(ADC) -- Capacitor digital-to-analog convertor (CDAC) -- Linearity calibration -- Digital background calibration -- Back-propagation algorithm -- Neural network; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2021.105113
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: A new digital background calibration scheme for non-linearity of successive approximation register (SAR) analog-to-digital convertor (ADC) is presented. Since non-linearity of high resolution SAR ADC is mainly caused by the difference between the real and ideal weights of capacitor digital-to-analog convertor (CDAC) with respect to the normalized-full-scale, calibration of weights of more significant bits is necessary when the resolution of SAR ADC comes to more than 12 bits. By using back-propagation algorithm to train the normalized real weight of more significant bits (MSBs) in neural network without any change in SAR ADC circuit design, the calibration table for each bit is implemented and updated in the digital domain without interrupting normal ADC process, which is used to correct the raw SAR code in the background to improve the performance of ADC, which is suitable for some detection applications in particular circumstances. In MATLAB simulation, the signal to noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) of a 14-bit with 1-bit redundancy SAR ADC model are improved to 85.59 ​dB and 97.27 ​dB from 56.65 ​dB to 77.07 ​dB using the proposed calibration scheme, at a standard deviation of a unit capacitor of 2%.