An FPGA-based implementation of corner detection and matching with outlier rejection. Issue 23 (2nd December 2018)

• Record Type: Journal Article
• Authors: Huang, Jingjin; Zhou, Guoqing; Zhang, Dianjun; Zhang, Guangyun; Zhang, Rongting; Baysal, Oktay
• Is Part Of: International journal of remote sensing. Volume 39:Issue 23(2018)
• Page Start: 8905
• Page End: 8933
• Publication Date: 2018-12-02
• Subjects: Remote sensing -- Periodicals; Télédétection -- Périodiques; 621.3678
• DOI: 10.1080/01431161.2018.1500728
• Languages: English
• ISSNs: 0143-1161

Abstract

ABSTRACT: To meet the high frame rate requirements of correct point correspondences with a sub-pixel precision, this paper first proposes a Field Programmable Gate Array (FPGA) architecture that consists of corner detection, corner matching, outlier rejection, and sub-pixel precision localisation. In the architecture, a combined Features from Accelerated Segment Test (FAST)+ Binary Robust Independent Elementary Features (BRIEF) algorithm is adopted for detection and matching with pixel precision, a combined algorithm of Slope-based Rejection (SR) and Correlation-Coefficient-based Rejection (CCR) is used to reject the outliers, and a gradient centroid-based algorithm is used for sub-pixel precision localisation. The whole FPGA architecture is implemented on a single FPGA platform (Xilinx XC72K325T). Five image datasets with different spatial resolutions, textures, lights, rotate angles, and viewpoints are used to evaluate the performance of the FPGA-based implementation. The experimental results show that (1) the SR and CCR algorithms are effective for outlier rejection; (2) a higher correct matching rate is achieved for the image pairs that cover artificial textures than for those that cover natural textures; (3) the proposed architecture is also suitable for image pairs with small change of lights, rotate angles, and viewpoints; (4) the speed of the FPGA-based implementation can reach 280 Frames Per Second (FPS), which is 35 times faster than the Personal Computer (PC)-based implementation; and (5) the usage of FPGA resources is acceptable for the selected FPGA platform. The speed and usage of the FPGA resources can be improved when the whole FPGA-based implementation is further optimised.