An improved asymmetrical multi‐level inverter topology with boosted output voltage and reduced components count. Issue 12 (6th April 2021)

• Record Type: Journal Article
• Authors: Arif, M Saad Bin; Mustafa, Uvais; Siddique, Marif Daula; Ahmad, Shahbaz; Iqbal, Atif; Ashique, Ratil Hasnat; Ayob, Shahrin bin
• Editors: Mekhilef, Saad; Yang, Yongheng; Siwakoti, Yam; Lam, Chi‐Seng; Sathik, Jagabar
• Is Part Of: IET power electronics. Volume 14:Issue 12(2021)
• Page Start: 2052
• Page End: 2066
• Publication Date: 2021-04-06
• Subjects: Power electronics -- Periodicals; 621.31705
• DOI: 10.1049/pel2.12119
• Languages: English
• ISSNs: 1755-4535

Abstract

Abstract: This paper presents an improved Multi‐level Inverter topology utilizing the concept of boosting‐capacitor and two DC sources with reduced switches count for generating 17‐level output. The topology employs 10 unidirectional switches including one bidirectional switch. Comparison with other recent topologies shows that the proposed topology employs a reduced number of devices and better performance. The topology combines the modularity of H‐Bridge with the boosting capacity of the switched capacitor topology. Special care is taken while designing the switching strategy for voltage balancing of the capacitors. The authors also have generalized the topology to produce 'n' level output. Relevant expressions are also formed and reported. Experimental validation, as well as simulation, is performed, and results are verified. Nearest level control is used as the modulation technique.