High‐speed and area‐efficient Sobel edge detector on field‐programmable gate array for artificial intelligence and machine learning applications. (10th May 2020)

• Record Type: Journal Article
• Authors: Sikka, Prateek; Asati, Abhijit R; Shekhar, Chandra
• Other Names: Srivastava Gautam guestEditor.; Hsu Ching‐Hsien (Robert) guestEditor.; Kumar Priyan Malarvizhi guestEditor.
• Is Part Of: Computational intelligence. Volume 37:Number 3(2021)
• Page Start: 1056
• Page End: 1067
• Publication Date: 2020-05-10
• Subjects: field‐programmable gate array -- hardware description language -- high‐level synthesis -- MATLAB HDL coder -- register transfer language -- Sobel edge detection -- Vivado; Artificial intelligence -- Periodicals; Computational linguistics -- Periodicals; 006.3
• DOI: 10.1111/coin.12334
• Languages: English
• ISSNs: 0824-7935

Abstract

Abstract: Sobel edge detector is an algorithm commonly used in image processing and computer vision to extract edges from input images using derivative of image pixels in x and y directions against surrounding pixels. Most artificial intelligence and machine learning applications require image processing algorithms running in real time on hardware systems like field‐programmable gate array (FPGAs). They typically require high throughput to match real‐time speeds and since they run alongside other processing algorithms, they are required to be area efficient as well. This article proposes a high‐speed and low‐area implementation of the Sobel edge detection algorithm. We created the design using a novel high‐level synthesis (HLS) design method based on application specific bit widths for intermediate data nodes. Register transfer level code was generated using MATLAB hardware description language (HDL) coder for HLS. The generated HDL code was implemented on Xilinx Kintex 7 field programmable gate array (FPGA) using Xilinx Vivado software. Our implementation results are superior to those obtained for similar implementations using the vendor library block sets as well as those obtained by other researchers using similar implementations in the recent past in terms of area and speed. We tested our algorithm on Kintex 7 using real‐time input video with a frame resolution of 1920 × 1080. We also verified the functional simulation results with a golden MATLAB implementation using FPGA in the loop feature of HDL Verifier. In addition, we propose a generic area, speed, and power improvement methodology for different HLS tools and application designs.