Area Efficient, High Speed EBCOT Architecture for Digital Cinema. (10th July 2012)

• Record Type: Journal Article
• Authors: Sarawadekar, Kishor; Banerjee, Swapna
• Other Names: Bhatia S. K. Academic Editor.; Hwang W.-L. Academic Editor.
• Is Part Of: ISRN signal processing. Volume 2012(2012)
• Publication Date: 2012-07-10
• Subjects: Signal processing -- Periodicals; Signal processing; Periodicals; 621.3822
• DOI: 10.5402/2012/714176
• Languages: English
• ISSNs: 2090-5041

Abstract

Abstract : Embedded block coding with optimised truncation (EBCOT) is a key algorithm in digital cinema (DC) distribution system. Though several high speed EBCOT architectures exist, all are not capable of meeting the DC specifications. To meet this challenge, the relationship between contents of a code block (CB) and context generation is studied. Our study reveals that it is difficult to predict number of contexts generated in a bit plane. Even the nature of number of contexts produced varies from CB to CB. In such a situation, it is difficult to ensure the frame rate requirement of DC. To avoid this uncertainty, a pass parallel, concurrent sample coding EBCOT architecture is proposed in this paper. It is capable of encoding one bit plane in 288 clock cycles under any circumstances. This design is prototyped on XC4VLX80-12 FPGA with multiple clock domains. After synthesizing, the bit plane coder (BPC) and MQ coder operate at 450 MHz and 123 MHz, respectively. In order to maintain synchronism among different clock domains, the BPC and MQ coder units are operated at 432 MHz and 108 MHz, respectively. This entails that the proposed design is capable of processing 2048 × 1080 size 57 DC frames in a second.