Performance evaluation of superjunction UMOS with dual polysilicon gate. (2021)

• Record Type: Journal Article
• Authors: Nautiyal, Payal; Naugarhiya, Alok; Verma, Shrish
• Is Part Of: Materials today. Volume 46:Part 10(2021)
• Page Start: 4546
• Page End: 4552
• Publication Date: 2021
• Subjects: Power MOSFET -- Superjunction -- Workfunction engineering -- Specific Resistance -- Electric Field -- Transconductance; Materials science -- Congresses -- Periodicals; 620.1
• DOI: 10.1016/j.matpr.2020.09.704
• Languages: English
• ISSNs: 2214-7853

Abstract

Abstract: A modified Superjunction (SJ) UMOS employing dual polysilicon material that is P + polysilicon and N + polysilicon on lower and upper portion of gate respectively is proposed in this paper. The proposed structure exploits the advantage of workfunction engineering at the gate electrode. The workfunction variation along the channel leads to increment in the transconductance and reduction in on resistance. The electrical characteristics of conventional SJ UMOS and proposed SJ UMOS have been simulated using ATLAS. The simulation results reveal 14.1% reduction in the resistance without any degradation in breakdown voltage. Further, transconductance and Baliga's Figure of Merit has also been calculated indicating 25% and 16.4% increment respectively for proposed structure signifying enhanced performance. The impact of temperature on the device behavior is also analyzed and it is suggested that the proposed device performs better than the conventional device even at higher temperature.