Adaptive Counter Clock Gated S-Box Transformation Based AES Algorithm of Low Power Consumption and Dissipation in VLSI System Design. Issue 1 (August 2021)

• Record Type: Journal Article
• Authors: Subramanian, K.; Venkatachalam, M.; Saroja, M.
• Is Part Of: Journal of physics. Volume 1979:Issue 1(2021)
• Publication Date: 2021-08
• Subjects: Advanced Encryption Standard (AES) -- Adaptive Counter-Clock (ACC) S-Box algorithm -- Field Programmable Gate Array (FPGA) -- Inverse Mix Column -- Inverse Sub Bytes (S-Box) -- Inverse Shift Row -- Verilog HDL -- Xilinx ISE 14.7 FPGA; Physics -- Congresses; 530.5
• DOI: 10.1088/1742-6596/1979/1/012066
• Languages: English
• ISSNs: 1742-6588

Abstract

Abstract: Advanced Encryption Standard (AES) is an effective algorithm trending today. According to the key length, it works efficiently. Here three types of key lengths are used such as 128, 192, and 256 bits. This paper introduced an Adaptive Counter-Clock (ACC) S-Box algorithm. This algorithm rectifies the error during data encryption and secure data from hackers. In this paper, we have done power consumption, power dissipation, and reduced the area size. Field Programmable Gate Array (FPGA) is utilized for hardware execution in the encryption process. Inverse Mix Column, Inverse Sub Bytes (S-Box) and Inverse Shift Row stages takes place in the decryption, so that the receiver can read the message in plain text which was sent by the sender. For this the receiver should have the same key used by the sender for encryption process. RTL coding is done using Verilog HDL, Xilinx ISE 14.7 FPGA will be used in the implementation.