A 4x4 modified 8 T SRAM cell array using power gating technique. (2021)

• Record Type: Journal Article
• Authors: Saranya, L.; Arvind, C.; Karthigaikumar, P.; Balachander, K.
• Is Part Of: Materials today. Volume 45:Part 2(2021)
• Page Start: 1820
• Page End: 1826
• Publication Date: 2021
• Subjects: SRAM -- Portable devices -- Low leakage power -- Battery devices -- Performance -- Sub threshold; Materials science -- Congresses -- Periodicals; 620.1
• DOI: 10.1016/j.matpr.2020.08.746
• Languages: English
• ISSNs: 2214-7853

Abstract

Abstract: Low power chip design is focused due to increase in demand of portable battery devices which is involved in day to day life. The memory plays an important role in all silicon on chip devices. SRAM's are most widely used memory in the VLSI devices due to it's better performance compared to DRAM. In Recent years SRAM, plays a dominant part in chip design and becomes the crucial research due to the high demand by the use of battery operated devices. To make the circuit more efficient the design should be successively operated with low leakage power at sub-threshold regions. A modified 8 T SRAM cell is designed and simulated using Tanner 13.1 EDA tool.