Design of area-efficient high speed 4 × 4 Wallace tree multiplier using quantum-dot cellular automata. (2021)

• Record Type: Journal Article
• Authors: Arunkumar Gudivada, A.; Jayaram Kumar, K.; Jajula, Srinivasa Rao; Siddani, Durga Prasad; Poola, Praveen Kumar; Vourganti, Varun; Panigrahy, Asisa Kumar
• Is Part Of: Materials today. Volume 45:Part 2(2021)
• Page Start: 1514
• Page End: 1523
• Publication Date: 2021
• Subjects: Nanotechnology -- Full adder -- QCA -- Wallace tree multiplier -- Quantum cell; Materials science -- Congresses -- Periodicals; 620.1
• DOI: 10.1016/j.matpr.2020.07.677
• Languages: English
• ISSNs: 2214-7853

Abstract

Abstract: Complementary metal oxide semiconductor (CMOS) devices are expected to face new challenges such as exponential current leakage, DIBL, hot carrier effects, and etc. at nano scale. Hence the CMOS technology is being supplanted by the nanotechnologies. Quantum-dot Cellular Automata (QCA) is key technology at nano scale which operates at tera hertz of speed. Comparing with the traditional CMOS technology, the QCA technology has low power consumption and high density. This technology also has a unique methodology such as "processing in wire" and "memory-in-motion". This work confers an area proficient, high speed full adder (FA) design with efficient clocking. The proposed full adder design comprises of 26 Quantum cells with delay of two clock phases, area occupancy of 0.03 µm 2 . This paper utilizes the unique characteristics of QCA and the proposed Wallace tree multiplier is implemented with the mentioned FA and is designed by using QCA Designer 2.0.3 tool.