Integration of III–V materials and Si-CMOS through double layer transfer process. (14th January 2015)

• Record Type: Journal Article
• Authors: Lee, Kwang Hong; Bao, Shuyu; Fitzgerald, Eugene; Tan, Chuan Seng
• Is Part Of: Japanese journal of applied physics. Volume 54:Number 3(2015:Mar.)
• Publication Date: 2015-01-14
• Subjects: Physics -- Periodicals; 621.05
• DOI: 10.7567/JJAP.54.030209
• Languages: English
• ISSNs: 0021-4922

Abstract

Abstract: A method to integrate III–V compound semiconductor and SOI-CMOS on a common Si substrate is demonstrated. The SOI-CMOS layer is temporarily bonded on a Si handle wafer. Another III–V/Si substrate is then bonded to the SOI-CMOS containing handle wafer. Finally, the handle wafer is released to realize the SOI-CMOS on III–V/Si hybrid structure on a common substrate. Through this method, high temperature III–V materials growth can be completed without the presence of the temperature sensitive CMOS layer, hence damage to the CMOS layer is avoided.