Scaling limit for InGaAs/GaAsSb heterojunction double-gate tunnel FETs from the viewpoint of direct band-to-band tunneling from source to drain induced off-characteristics deterioration. (21st June 2016)

• Record Type: Journal Article
• Authors: Lin, Wenbo; Iwata, Shinjiro; Fukuda, Koichi; Miyamoto, Yasuyuki
• Is Part Of: Japanese journal of applied physics. Volume 55:Number 7(2016:Jul.)
• Publication Date: 2016-06-21
• Subjects: Physics -- Periodicals; 621.05
• DOI: 10.7567/JJAP.55.070303
• Languages: English
• ISSNs: 0021-4922

Abstract

Abstract: In this paper, we propose a method to classify the tunneling currents using simulations. The main objective is to investigate the effects of the direct source-to-drain tunneling, which is undesirable, in the case of devices with extremely short channels. We performed the classification of tunneling currents in InGaAs/GaAsSb heterojunction double-gate tunnel FETs based on this method, and we found that the direct-tunneling component increased dramatically in short-channel cases. The channel length must be 20 nm or longer, in case of InGaAs/GaAsSb heterojunction double-gate tunnel FETs, to limit the off-current within 10 pA/µm, which is required as per the ITRS LP.