VLSI Design for High‐Precision Three‐Dimensional Depth Perception Chip. Issue 3 (1st May 2021)

• Record Type: Journal Article
• Authors: Chenyang, GE; Huimin, YAO; Yanhui, ZHOU; Pengchao, DENG
• Is Part Of: Chinese journal of electronics. Volume 30:Issue 3(2021)
• Page Start: 556
• Page End: 560
• Publication Date: 2021-05-01
• Subjects: 3D depth perception -- structure light coding -- VLSI -- ASIC; Electronics -- Periodicals; Electronics -- China -- Periodicals; Electronics; China; Periodicals; 621.38105
• DOI: 10.1049/cje.2021.04.009
• Languages: English
• ISSNs: 1022-4653

Abstract

Abstract : This paper presents a Very large scale integration (VLSI) design method for Three‐dimensional (3D) depth perception chip based on infrared coding structure light. The primary sub‐modules on the chip contain the speckle pattern preprocessing module, block‐matching disparity estimation, depth mapping and post‐processing. The chip employs pipelining technology, and after Application specific integrated circuit (ASIC) verification, it proves that our chip has more advantages in performance of depth precision (12bits, 1mm @ 1m), image resolution (1280×960), time delay (less than 17ms), range limit (0.4~6m). It also can generate more stable and smooth depth map in real‐time, which can be used in 3D recognition, motion capture or scene perception.