Gate mapping impact on variability robustness in FinFET technology. (September 2019) - Brendler, L.H.; Zimpeck, A.L.; Meinhardt, C.; Reis, R.A.L.
Abstract: Traditionally, complex gates are adopted to reduce area, delay and power consumption. However, they can introduce challenges related to a robustness that might be avoided with more regular and basic cell rules. This work shows the relation between gate mapping and process variability robustness in FinFET technology, exploring for the same circuit, a complex-gate design and a basic gates one. The transistor arrangement adopted can vary by up to 30% the delay robustness, around 18% the robustness to the power consumption and 25% the Power-Delay-Product deviation. Highlights: The process variability effects need to be considered in variation-tolerant circuit design. The work explores variability effects and Gate mapping, evaluating different transistor arrangements for the C17 Benchmark. The arrangement adopted varies around 30% and 18% the delay and power robustness considering the process variability impact. The adoption of basic cells results in up to 25% lower Power-Delay-Product deviations than the complex arrangement. The choice of a particular arrangement is of the utmost importance to increasing the process variability robustness.