ESD-failure of E-mode GaN HEMTs: Role of device geometry and charge trapping. (September 2019) - Canato, E.; Meneghini, M.; Nardo, A.; Masin, F.; Barbato, A.; Barbato, M.; Stockman, A.; Banerjee, A.; Moens, P.; Zanoni, E.; Meneghesso, G.
Abstract: We investigate the robustness of E-mode GaN HEMTs under ESD testing; specifically, we focus on three aspects, i.e. the impact of gate bias on TLP failure voltage, the role of device geometry (with focus on gate length), and the difference in failure voltage when tests are carried out under UV illumination. The results demonstrate that: (i) when the transistors are tested in semi-on and on-state (4 V < VGS < 6 V), failure occurs due to a current-dependent process and failure takes place at a random position along the gate finger, as demonstrated by optical inspection; (ii) gate geometry strongly impacts on TLP stability; specifically, devices with larger gate length have a better robustness, possibly due to the lower drain current (higher on-resistance) and the lower power dissipation. (iii) We find that under UV light the TLP robustness is slightly improved. This is ascribed to a "beneficial" effect of traps; however, the effect is much less than in previous reports, possibly due to a much better epitaxial quality. Highlights: SOA limits at wafer level to study the dependence of failure voltage on gate and drain voltage using a TLP system; We focus on the impact of gate bias, the role of device geometry, and the difference when tests are carried out under UV; By increasing gate bias, a lower TLP failure threshold is observed. TLP-SOA indicates a current failure mechanism Devices with longer gate have better stability, due to the lower current level and power dissipation; Similar behaviour when tests are done in dark and UV due to good epitaxial quality of devices that have a low density of traps.