A computational study of the effect of bond pad thickness on the polysilicon piezoresistivity due to wafer level probing. (September 2019) - Mane, Sanjay Shrirang; Sethu, Raj Sekar; Bergmann, Lars; Erstling, Marco; Soon, Kok Heng
Abstract: Polysilicon is an integral part of many devices in all CMOS processes. Circuit Under Pad (CUP) devices are required to have consistent and accurate electrical performance just like any other device. This paper presents an investigation on stress impact of probe insertions on two bond pad metal options (METMID and METTHK) on a polysilicon resistor placed under the bond pad. Wafer level probing results in residual stress on both Back End Of Line (BEOL) as well as Front End Of Line (FEOL) structures. This residual stress would impact the electrical properties of the polysilicon material used in such devices. In this study, such electrical impact is measured in terms of change in resistance (piezoresistivity) of a polysilicon resistor which was placed underneath the bond pads. A commercial finite element analysis software (Comsol Multiphysics) was used to predict the stress distribution in the polysilicon device, followed by experimental validation of the electrical resistance. It was observed that the bond pad thickness can influence the residual stress which in turn causes a change in resistance after wafer level probing. However, for each bond pad thickness, multiple probe insertions did not significantly change the resistance of the device placed under the bond pad.