Radiation hardening efficiency of gate sizing and transistor stacking based on standard cells. (September 2019) - Aguiar, Y.Q.; Wrobel, F.; Guagliardo, S.; Autran, J.-L.; Leroux, P.; Saigné, F.; Touboul, A.D.; Pouget, V.
Abstract: Soft error mitigation schemes inherently lead to penalties in terms of area usage, power consumption and/or performance metrics. This work provides a radiation hardening efficiency analysis of two possible selective node hardening based on standard cells: Gate Sizing and Transistor Stacking. The impact on the Single-Event Transient (SET) cross-section, layout area and leakage current is discussed. The results indicate that both techniques provide the same area overhead and high efficiency for low particle linear energy transfer. Further, although transistor stacking exhibits lower static power consumption, gate sizing still presents the best trade-off between area, performance and reliability. However, the hardening efficiency of transistor stacking is strongly dependent on the input signal of the gate. Thus, according to the application, this technique can possibly outperform gate sizing.