Process variation-aware gate sizing with fuzzy geometric programming. (September 2019)

• Record Type: Journal Article
• Authors: Ghavami, Behnam; Raji, Mohsen; Rasaizadi, Ramin; Mashinchi, Mashaallah
• Is Part Of: Computers & electrical engineering. Volume 78(2019)
• Page Start: 259
• Page End: 270
• Publication Date: 2019-09
• Subjects: Digital circuit -- Gate sizing -- Fuzzy geometric optimization -- Power consumption -- Process variation; Computer engineering -- Periodicals; Electrical engineering -- Periodicals; Electrical engineering -- Data processing -- Periodicals; Ordinateurs -- Conception et construction -- Périodiques; Électrotechnique -- Périodiques; Électrotechnique -- Informatique -- Périodiques; Computer engineering; Electrical engineering; Electrical engineering -- Data processing; Periodicals; Electronic journals; 621.302854
• DOI: 10.1016/j.compeleceng.2019.07.015
• Languages: English
• ISSNs: 0045-7906

Abstract

Abstract: Limitations of manufacturing process in nanometer dimensions have led to large discrepancies between the circuit design and the manufactured chip known as process variation. In this paper, a new gate sizing method based on fuzzy geometric optimization approach is introduced for power minimization of digital circuits subjected to timing constraints under process variations. In the proposed geometric optimization approach, an accurate gate delay model is applied in which the delay variation is represented by fuzzy numbers; therefore, the subsequent optimization problem is a fuzzy geometric programing problem. In order to efficiently solve the fuzzy geometric programing problem, firstly, the problem is converted into a fuzzy linear programming problem and then, using the expected value and Mellin transform, it is converted into a non-fuzzy problem which is solved by traditional solution techniques. Experimental results show that, the proposed technique achieve more power reduction compared to a fuzzy linear programming method.