Effect of the thermal stress on the defect evolution at GaAs/Si wafer bonding with a-Ge intermediate layer. (27th July 2021) - Li, Zongpei; Huang, Donglin; Jiao, Jinlong; Wang, Ziwei; Li, Cheng; Huang, Wei; Ke, Shaoying; Chen, Songyan
Abstract: In this paper, the bonding of GaAs wafer and Si wafer is achieved by introducing an amorphous Ge as the intermediate layer. Dislocations are observed on the GaAs surface when the GaAs/Si bonded wafers are annealed at 150 °C. The dislocation density is found to increase with the increase of the annealing temperature (from 150 °C to 350 °C). This feature can be explained by the increase of the thermal stress in the GaAs wafer due to the thermal mismatch between GaAs and Si wafers. With higher annealing temperature, such as 300 °C and 350 °C, some pits which originate from the partial cracking of GaAs surface are observed at the boundary of the bonded and unbonded regions. According to the stress simulation, the thermal stress at the bonding interface increases rapidly and reaches its maximum near the boundary of the bonded and unbonded regions, leading to the cracking of GaAs surface (formation of pits). In addition, large numbers of dislocations are generated near the pits. This may be attributed to the reduction of the nucleation energy of dislocations.