Design of node separated triple-node-upset self-recoverable latch. (August 2021)

• Record Type: Journal Article
• Authors: Huang, Zhengfeng; Cao, Di; Cui, Jianguo; Lu, Yingchun; Liang, Huaguo; Ouyang, Yiming; Ni, Tianming; Li, Zhenmin
• Is Part Of: Microelectronics journal. Volume 114(2021)
• Publication Date: 2021-08
• Subjects: Circuit reliability -- Radiation hardened by design -- Triple-node-upset -- Self-recovery; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2021.105111
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: With the continuous scaling of IC technology, latches becomes more vulnerable to double-node-upset (DNU) and triple-node-upset (TNU). The node separated (NS) method applied for DNU hardening has not been used for TNU hardening to effectively reduce the probability of TNU occurrence, resulting in excessive power consumption, delay and area overhead of TNU hardening. This paper proposes a low-overhead TNU self-recoverable latch, named Node Separated Triple-node-upset Self-recoverable Latch (NS-TSL). NS-TSL includes four N-type stacked structures, four P-type stacked structures, a clock gating based inverter, and a high-speed transmission path. Based on a physical flip mechanism that makes sensitive nodes flip in one direction and multiple feedback mechanism, NS-TSL can realize TNU self-recovery. Simulation results demonstrate that compared with the other six TNU hardened latches, NS-TSL reduces the delay by 62.24%, the power consumption by 59.96%, the power delay product by 84.04%, and the area by 27.97% on average. Moreover, NS-TSL is insusceptible to temperature and voltage variations.