Low mismatch high-speed charge pump for high bandwidth phase locked loops. (August 2021)

• Record Type: Journal Article
• Authors: Lad Kirankumar, H.; Rekha, S.; Laxminidhi, Tonse
• Is Part Of: Microelectronics journal. Volume 114(2021)
• Publication Date: 2021-08
• Subjects: High bandwidth phase locked loop -- High speed charge pump -- Mismatch current -- Reference spur; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2021.105156
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: This paper presents a low mismatch high-speed charge pump for high bandwidth phase locked loop (PLL). A novel mismatch compensation technique is used for reducing the current mismatch without having any extra area and power overhead. Proposed circuit is designed for 100 μ A charge pump current ( I CP ) and it achieves less than 1% mismatch current across all process corners for an output voltage compliance range of 0.2–1 V. A prototype circuit of 1 GHz PLL is designed in 65 nm CMOS technology for testing the proposed charge pump. It achieves −81.2 dBc spur-level at reference frequency of 250 MHz. In locked condition of the PLL, proposed charge pump consumes 176 μ W power from 1.2 V supply including the reference current. Area occupied by proposed design is 72 × 35 μ m 2 .