Placement-guided pin layout substitution for routability optimization. (August 2021)

• Record Type: Journal Article
• Authors: Chang, Jia-Hong; Fang, Shao-Yun
• Is Part Of: Microelectronics journal. Volume 114(2021)
• Publication Date: 2021-08
• Subjects: Pin layout substitution -- Routability optimization; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2021.105151
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: The pin access of standard cells plays a critical role at the detailed routing stage to determine routability, and various evaluation models for pin accessibility have been proposed in previous works. However, to meet more complicated design rules and to enhance routing flexibility in sub-10nm technology nodes, the cell architecture has been greatly revised, where power and ground rails are moved up to the Metal 2 (M2) layer, making the one-dimensional pins on M1 extendable, and thus more external access points could be available for pin access. As a result, merely considering the pin length and the horizontally adjacent pins and environment to evaluate pin accessibility in existing works would be seriously deficient. In this paper, we redesign the cell library of the 2015 ISPD placement contest benchmark suite to meet the special cell architecture. Then, we propose the first pin layout substitution flow for the new cell design style based on a fixed cell placement result by honoring an initial routing solution. Our aim is to reduce the number of design rule violations (DRVs) by maximizing the routing resource of inaccessible pins. Experimental results show that the proposed flow can effectively and efficiently reduce the number of DRVs compared to previous works, which achieves 21.86% DRV reduction on average and improves all the testcases by only rerouting the nets suffering from DRVs.