Multi‐precision binary multiplier architecture for multi‐precision floating‐point multiplication. Issue 5 (11th March 2021)

• Record Type: Journal Article
• Authors: Tomar, Geetam Singh; George, Marcus Llyode; Tomar, Abhineet Singh
• Is Part Of: IET circuits, devices & systems. Volume 15:Issue 5(2021)
• Page Start: 455
• Page End: 464
• Publication Date: 2021-03-11
• Subjects: Electronic circuits -- Periodicals; Electronic systems -- Periodicals; 621.381505
• DOI: 10.1049/cds2.12041
• Languages: English
• ISSNs: 1751-858X

Abstract

Abstract: Arithmetic logic units (ALUs) are core components of processing devices that perform required arithmetic and logical operations such as multiplication, division, addition, subtraction, and squaring. The multiplication operation is frequently used in ALUs in engineering applications such as signal processing, video processing and image processing for which floating‐point multiplication is an important component. The dynamic range of numbers represented by floating‐point arithmetic is very large compared with that of fixed‐point numbers of the same bit width. A mantissa similarity investigator (MSI)–interfaced multi‐precision binary multiplier architecture is developed and can be used in data‐intensive applications that require variable precision, high throughput and low delay. This architecture can be configured to operate in single‐, double‐, quadruple‐ and octuple‐precision modes for mantissa multiplication according to the IEEE 754 standard for floating‐point numbers. The system produces increased throughput and utilises mantissa similarity to reduce system delay. The system was synthesised for a variety of field‐programmable gate array targets using Xilinx ISE Design Suite 14.7, and performance was simulated using that suite's ISim simulator.