Area Optimized FPGA-Based Implementation of The Sobel Compass Edge Detector. (7th March 2013)

• Record Type: Journal Article
• Authors: Singh, Sanjay; Saini, Anil Kumar; Saini, Ravi; Mandal, A. S.; Shekhar, Chandra; Vohra, Anil
• Other Names: Alchanatis V. Academic Editor.; Nikolaidis A. Academic Editor.
• Is Part Of: ISRN machine vision. Volume 2013(2013)
• Publication Date: 2013-03-07
• Subjects: Computer vision -- Periodicals; Computer vision; Periodicals; Electronic journals; 006.37
• DOI: 10.1155/2013/820216
• Languages: English
• ISSNs: 2090-7796

Abstract

Abstract : This paper presents a new FPGA resource optimized hardware architecture for real-time edge detection using the Sobel compass operator. The architecture uses a single processing element to compute the gradient for all directions. This greatly economizes on the FPGA resources' usages (more than 40% reduction) while maintaining real-time video frame rates. The measured performance of the architecture is 50 fps for standard PAL size video and 200 fps for CIF size video. The use of pipelining further improved the performance (185 fps for PAL size video and 740 fps for CIF size video) without significant increase in FPGA resources.