Flexible design of wide‐pipeline‐based WiMAX QC‐LDPC decoder architectures on FPGAs using high‐level synthesis. Issue 11 (1st May 2014)

• Record Type: Journal Article
• Authors: Andrade, J.; Falcao, G.; Silva, V.
• Is Part Of: Electronics letters. Volume 50:Issue 11(2014)
• Page Start: 839
• Page End: 840
• Publication Date: 2014-05-01
• Subjects: parity check codes -- WiMax -- decoding -- error statistics -- high level synthesis -- field programmable gate arrays -- parallel processing -- VLSI -- fixed point arithmetic; flexible design -- wide‐pipeline‐based WiMAX QC‐LDPC decoder architecture -- FPGA -- low‐density parity‐check decoder approach -- worldwide interoperability for microwave access standard -- WiMAX standard -- 802.16e -- field‐programmable gate array -- high‐level synthesis tool -- wide‐pipeline architecture -- optimised open computing language -- OpenCL‐based kernels -- single‐instruction multiple data -- SIMD -- parallelism level -- decoding throughput -- very large‐scale integration -- 8‐bit fixed‐point arithmetic -- bit error rate performance -- error floor region; Electronics -- Periodicals; 621.381
• DOI: 10.1049/el.2013.3411
• Languages: English
• ISSNs: 0013-5194

Abstract

Abstract : A novel wide‐pipeline low‐density parity‐check (LDPC) decoder approach for the worldwide interoperability for microwave access (WiMAX) standard (802.16e) is proposed for execution on field‐programmable gate arrays (FPGAs), using a high‐level synthesis tool to reduce the development effort and design validation time that generates a wide‐pipeline architecture. Optimised open computing language (OpenCL)‐based kernels are developed and the integration of distinct configurations of single instruction multiple data and compute units to increase the level of parallelism are analysed. The decoding throughput surpasses the minimal requirements of 75 Mbit/s, a key figure of merit that ranks the design with other very large‐scale integration‐based approaches. Furthermore, extra precision is deployed with 8‐bit fixed‐point arithmetic, delivering superior bit error rate performance and lower error floor regions.