Lookup table‐based negative‐bias temperature instability effect and leakage power co‐optimization using genetic algorithm approach. (3rd May 2021)

• Record Type: Journal Article
• Authors: Bhattacharjee, Abhishek; Sahu, Dheeraj Kumar; Pradhan, Sambhu Nath
• Is Part Of: International journal of circuit theory and applications. Volume 49:Number 7(2021)
• Page Start: 1902
• Page End: 1915
• Publication Date: 2021-05-03
• Subjects: NBTI -- leakage power -- genetic algorithm -- input vector control -- low power VLSI; Electric circuit analysis -- Periodicals; 621.319205
• DOI: 10.1002/cta.3038
• Languages: English
• ISSNs: 0098-9886

Abstract

Summary: As a result of continuous scaling of transistors, negative bias temperature instability (NBTI) has become a serious reliability concern which causes the device to degrade over its lifetime. Similarly, leakage power also remains a key issue in deep submicron technologies. Both NBTI‐related delay degradation and standby time leakage power depend strongly on the circuit's input patterns. The input vector control (IVC) technique can be used for mitigating both NBTI‐related delay degradation and leakage power. However, the input vectors with the least NBTI‐induced degradation may not be the same ones with the least leakage power in any circuit; therefore, co‐optimization is needed to minimize leakage and NBTI‐induced degradation. In this paper, a genetic algorithm (GA)‐based approach is presented to co‐optimize both NBTI‐related performance degradation and also leakage power. We are also presenting a trade‐off analysis by giving different weightage to the NBTI effect and leakage power. Simulation results applied on ISCAS'85 benchmark circuits illustrate that on average our proposed technique saves up to 21.85% and 17.68% circuit performance degradation and the leakage power, respectively. Abstract : In this paper, we present a Genetic algorithm (GA) based approach to co‐optimize NBTI related delay degradation as well as the leakage power. We are also presenting a trade‐off analysis by giving different weightage to the NBTI effect and leakage power. Simulation results on ISCAS'85 benchmark circuits show on average our proposed technique saves up to 21.85% and 17.68% circuit performance degradation and leakage power respectively. ​