Development of a cost‐effective circuit hardware architecture for brushless direct current motor driver. (7th April 2021)

• Record Type: Journal Article
• Authors: Mishra, Pratikanta; Banerjee, Atanu; Ghosh, Mousam; Gogoi, Sushanta; Dutta, Rukmi
• Is Part Of: International journal of circuit theory and applications. Volume 49:Number 7(2021)
• Page Start: 2183
• Page End: 2198
• Publication Date: 2021-04-07
• Subjects: application‐specific integrated circuit (ASIC) -- brushless DC (BLDC) motor -- digital pulse‐width modulation (DPWM) -- field‐programmable gate array (FPGA); Electric circuit analysis -- Periodicals; 621.319205
• DOI: 10.1002/cta.3011
• Languages: English
• ISSNs: 0098-9886

Abstract

Summary: A dual‐duty digital pulse‐width modulation (DDPWM) technique‐based cost‐effective control hardware architecture for brushless DC (BLDC) motor drive is reported in this paper. DDPWM control technique involves reduced computational complexity, which is beneficial in on‐chip area and power dissipation reduction. Simple Hall sensor‐based speed calculation and commutation circuits were also incorporated in the hardware to reduce the chip area further. The edge detection‐based speed calculation circuit was designed to be tolerant of any external noise or glitch in the Hall sensor signal. The proposed hardware architecture was implemented on the field‐programmable gate array (FPGA) and application‐specific integrated circuit (ASIC) platform using TSMC 180‐nm technology library. The ability of the integrated circuit (IC) for resource utilization reduction was validated by comparing the FPGA‐implemented architecture with the existing literature. The FPGA‐implemented architecture was also examined in real‐time using an experimental prototype BLDC motor setup. The drive response with dynamic load and speed variations, speed control precision, and glitch tolerant speed calculation is reported in the paper. The ASIC implementation demonstrates that the developed architecture sampled at 50 MHz is highly effective in the gate count and power dissipation reduction compared to the standard PI controller‐based width modulated pulse generation hardware architecture. Abstract : A dual‐duty digital pulse‐width modulation technique‐based cost‐effective hardware architecture for BLDC motor drive is reported in this paper. Simple Hall sensor‐based speed calculation and commutation circuits are incorporated in the hardware for chip compactness. The edge detection‐based speed calculation circuit is tolerant to Hall sensor signal glitches. The proposed hardware architecture was implemented on field‐programmable gate array (FPGA) and application‐specific integrated circuit (ASIC) platform using TSMC 180‐nm technology library. The FPGA‐implemented architecture was examined in real‐time using an experimental prototype.