A low‐error, memory‐based fast binary antilogarithmic converter. (28th February 2021)

• Record Type: Journal Article
• Authors: Guna Sekhar Sai Harsha, L.; Jammu, Bhaskara Rao; Samoju, Visweswara Rao; Veeramachaneni, Sreehari; Mohammad S, Noor
• Is Part Of: International journal of circuit theory and applications. Volume 49:Number 7(2021)
• Page Start: 2214
• Page End: 2226
• Publication Date: 2021-02-28
• Subjects: division -- logarithmic arithmetic -- logarithmic converters -- logarithmic number system -- multiplication; Electric circuit analysis -- Periodicals; 621.319205
• DOI: 10.1002/cta.2981
• Languages: English
• ISSNs: 0098-9886

Abstract

Summary: The ever‐increasing need for high‐performance signal processing blocks in avionics, machine learning (ML), IoT, neural networks, etc., has made the logarithmic arithmetic's as the front runner in advanced processors. The complex arithmetic operations such as multiplication and division can be easily performed in the logarithmic domain as they become addition and subtraction operations, respectively. However, the challenge is to perform the logarithmic and anti‐logarithmic conversions and to optimize the trade‐off between hardware complexity and accuracy. In this work, we propose a 32‐bit antilogarithmic converter, for/using Mitchell's algorithm. The obtained results are corrected using the weighted average method. The correction terms are stored and selected using 32 × 8 ROM to decreases the computational speed and hardware complexity of the antilogarithmic converter. The proposed antilogarithmic converter has a maximum error percentage of 1.199%, which is 6.147% for Mitchell's algorithm while maintaining the hardware metrics close to Mitchell's algorithm. Abstract : The use of logarithms minimized the computations for multiplication and division to the stage of addition and subtraction. Still, the logarithm and antilogarithm converters are the barriers as they require massive hardware. This paper presents a weighted average method to improve Mitchell's antilogarithm converter's accuracy with less hardware complexity. The experimental result shows that the proposed method controls the trade‐off between hardware and performance.