Accessing register spaces in FPGAs within the ATLAS DAQ scheme via the SCA eXtension. (30th June 2021)

• Record Type: Journal Article
• Authors: Bakalis, C.; Alexopoulos, T.; Grayzman, I.; Lee, L.; Levinson, L.; Polychronakos, V.
• Is Part Of: Journal of instrumentation. Volume 16:Number 6(2021)
• Publication Date: 2021-06-30
• Subjects: Detector control systems (detector and experiment monitoring and slow-control systems, architecture, hardware, algorithms, databases) -- Data acquisition concepts -- Digital electronic circuits; Scientific apparatus and instruments -- Periodicals; 502.84
• DOI: 10.1088/1748-0221/16/06/P06041
• Languages: English
• ISSNs: 1748-0221

Abstract

Abstract: The foreseen upgrades of the Large Hadron Collider (LHC) are expected to increase the required throughput of the front-end and back-end electronics that support the readout of the LHC detectors. Therefore, the complexity of the electronics systems will be increased as well. An example of this is the electronics system of the New Small Wheel (NSW) upgrade of the ATLAS detector, which will be comprised of a number of Field-Programmable Gate Arrays (FPGAs), and Application-Specific Integrated Circuits (ASICs). These ASICs will be configured and monitored by the Slow Control Adapter (SCA), another ASIC designed for this purpose. The Slow Control Adapter eXtension (SCAX) on the other hand, is an FPGA module designed to support FPGA systems that are part of the ATLAS electronics scheme by reading and writing their configuration parameters and status indicators. SCAX emulates both the I2C interface of the SCA used to access the NSW ASICs, as well as the communication protocol implemented between the SCA and the back-end infrastructure. It thereby enables using the same OPC-UA server and back-end software suite that support the ASICs, to also interface with the FPGAs that are part of the same system. This work describes the context of the SCAX's implementation, alongside architectural considerations of the module, features, and techniques to validate its hardware implementation across a variety of FPGA devices.