CMV reduction in a three‐to‐seven phase direct matrix converter using SVPWM. Issue 8 (31st May 2019)

• Record Type: Journal Article
• Authors: Rahman, Khaliqur; Al‐Emadi, Nasser; Al‐Hitmi, Mohammad; Iqbal, Atif
• Is Part Of: IET electric power applications. Volume 13:Issue 8(2019)
• Page Start: 1219
• Page End: 1228
• Publication Date: 2019-05-31
• Subjects: matrix convertors -- PWM invertors -- field programmable gate arrays -- leakage currents -- switching convertors -- motor drives -- electric drives; high‐frequency leakage currents -- motor bearing -- PWM methods -- motor drives -- reduction/elimination -- modulation technique -- space‐vector approach -- three‐to‐seven‐phase direct matrix converter -- CMV reduction -- zero‐voltage vectors -- space‐vector PWM -- SVPWM technique -- three‐to‐seven phase direct matrix converter -- pulse‐width modulation‐controlled modern electric drives -- serious problems -- common‐mode voltage; Electric power -- Periodicals; Electric power systems -- Periodicals; 621.305
• DOI: 10.1049/iet-epa.2018.5188
• Languages: English
• ISSNs: 1751-8660

Abstract

Abstract : The pulse‐width modulation (PWM)‐controlled modern electric drives causes some serious problems such as the generation of common‐mode voltage (CMV) and high d v /d t . The CMV might cause high‐frequency leakage currents that flow through the possible path that is bearing of the motor. Thus, the flow of current through the motor bearing leads to its premature failure. One of the main challenges in developing PWM methods for control of motor drives is the problem of CMV and its reduction/elimination. In this study, a modulation technique based on space‐vector approach is developed to reduce the CMV in a three‐to‐seven‐phase direct matrix converter. CMV reduction becomes possible by selecting suitable zero‐voltage vectors for a specific duration and the use of a selected set of active vectors for the output voltage synthesis. The proposed space‐vector PWM (SVPWM) for the reduction of CMV is performed with a seven‐phase R–L load to show the viability of the proposed technique. The proposed SVPWM technique is implemented experimentally in dSPACE working in conjunction with field‐programmable gate array processor board using a system generator. Hardware results that validate the proposed control algorithm are discussed.