A 312 ps response‐time LDO with enhanced super source follower in 28 nm CMOS. Issue 16 (1st August 2016) - Lu, Yan; Li, Cheng; Zhu, Yan; Huang, Mo; U, Seng‐Pan; Martins, Rui P.
Abstract : High quality fully integrated power supplies could notably improve the performances of the noise‐sensitive building block in the UWB communication systems. Double buffers are inserted into the cascode flipped‐voltage‐follower (FVF) topology to enable designing the dominant pole at the output node for better power supply rejection (PSR) and less voltage variation during load transient. An enhanced super source follower (E‐SSF) is proposed to further reduce the output impedance of the buffer that drives the power transistor. The FVF‐based low dropout regulator (LDO) with E‐SSF achieves a worst‐case PSR of −18.9 dB across the full spectrum and a transient response time of 312 ps. The proposed LDO is designed in a 28 nm CMOS process and consumes 100 μA quiescent current with 1.0 V input and 0.8 V output voltages. In total, 120 pF on‐chip capacitors are used for filtering.