Performance improvement of timing and power variations due to random dopant fluctuation in negative‐capacitance CMOS inverters. Issue 6 (9th September 2020)

• Record Type: Journal Article
• Authors: Zhang, Kai; Lü, Weifeng; Si, Peng; Zhao, Zhifeng; Yu, Tianyu
• Is Part Of: IET circuits, devices & systems. Volume 14:Issue 6(2020)
• Page Start: 908
• Page End: 914
• Publication Date: 2020-09-09
• Subjects: CMOS digital integrated circuits -- invertors -- low‐power electronics -- power integrated circuits; performance improvement -- power variations -- negative‐capacitance CMOS inverters -- random dopant fluctuation‐induced variations -- transition delay -- viscosity coefficient -- baseline CMOS -- low‐power device -- propagation delay -- steeper transient subthreshold swing -- threshold voltage -- timing parameters -- high‐to‐low transition -- low‐to‐high transition -- negative capacitance effect -- static DC power -- FE thickness -- low‐power CMOS digital circuits -- RDF‐induced timing variations -- NC‐CMOS inverter -- technology‐aided design simulation; Electronic circuits -- Periodicals; Electronic systems -- Periodicals; 621.381505
• DOI: 10.1049/iet-cds.2020.0101
• Languages: English
• ISSNs: 1751-858X

Abstract

Abstract : In this study, we compared the timing and its random dopant fluctuation (RDF)‐induced variations in nanometre conventional and negative‐capacitance CMOS (NC‐CMOS) inverters. The authors found that the transition delay in the NC‐CMOS inverter exhibits a strongly dependence on the viscosity coefficient ( ρ ) of the ferroelectric (FE). Only NC‐CMOS using sufficiently low ρ with smaller response time to baseline CMOS can be considered as a low‐power device with a smaller propagation delay. Due to the steeper transient subthreshold swing and lower threshold voltage ( V th ), the timing parameters, e.g. rise time, fall time, high‐to‐low transition, low‐to‐high transition, and propagation delay were all reduced. Furthermore, RDF‐induced timing variations can be effectively suppressed by the negative capacitance effect provided by the FE capacitor and the fluctuation of static DC power also drops, and this immunity to RDF‐induced timing variations increases with increasing FE thickness ( T FE ). Our analysis was verified by technology‐aided design simulation and can provide useful insights into future studies of low‐power CMOS digital circuits.