0.5–4.4 Gbit/s PAM4/NRZ dual‐mode transceiver with 0.6 V near‐ground NMOS driver for low‐power memory interface. Issue 11 (1st May 2018)

• Record Type: Journal Article
• Authors: Min, K.; Oh, T.
• Is Part Of: Electronics letters. Volume 54:Issue 11(2018)
• Page Start: 684
• Page End: 685
• Publication Date: 2018-05-01
• Subjects: transceivers -- low‐power electronics -- CMOS memory circuits -- driver circuits; PAM4‐NRZ dual‐mode input‐output transceiver scheme -- near‐ground NMOS driver -- low‐power memory interface application -- near‐ground mode -- channel loss condition -- bidirectional two channel transceiver -- CMOS process -- bit rate 0.5 Gbit/s to 4.4 Gbit/s -- voltage 0.6 V -- size 45 nm -- power 2.24 mW -- power 2.78 mW; Electronics -- Periodicals; 621.381
• DOI: 10.1049/el.2018.0871
• Languages: English
• ISSNs: 0013-5194

Abstract

Abstract : An efficient dual‐mode input and output transceiver scheme is proposed. The transceiver can achieve the data speed from 0.5 up to 4.4 Gbit/s with 0.6 V supply voltage and can support the near‐ground mode for low‐power memory interface application. The transceiver can transmit both PAM4/NRZ signals flexibly depending on the channel loss conditions. The prototype bi‐directional two‐channel transceiver is implemented in 45 nm CMOS process and occupies 0.0516 mm 2 chip area. The IP shows power consumption of 2.24/2.78 mW during 4.4 Gbit/s PAM4/NRZ mode operation, each, respectively.