55 dB DC gain, robust to PVT single‐stage fully differential amplifier on 45 nm SOI‐CMOS technology. Issue 10 (1st May 2014)

• Record Type: Journal Article
• Authors: Gómez, H.; Espinosa, G.
• Is Part Of: Electronics letters. Volume 50:Issue 10(2014)
• Page Start: 737
• Page End: 739
• Publication Date: 2014-05-01
• Subjects: silicon -- elemental semiconductors -- differential amplifiers -- silicon‐on‐insulator -- operational amplifiers -- CMOS analogue integrated circuits -- UHF amplifiers -- UHF integrated circuits -- integrated circuit design; PVT single‐stage fully differential amplifier -- SOI‐CMOS technology -- single‐stage operational transconductance amplifier -- self‐cascode transistor -- current shunt stage -- silicon on insulator -- minimum gain bandwidth product -- GBW product -- phase margin -- PM -- simulated transient behaviour -- slew rate -- SR -- gain 55 dB -- size 45 nm -- bandwidth 540 MHz -- time 7 ns -- capacitance 0.3 pF -- Si; Electronics -- Periodicals; 621.381
• DOI: 10.1049/el.2014.0883
• Languages: English
• ISSNs: 0013-5194

Abstract

Abstract : The design of a single‐stage operational transconductance amplifier is presented, which uses self‐cascode transistors and current shunt stages to improve its DC gain. The proposed amplifier is implemented in a standard 45 nm silicon on insulator CMOS process. Simulation results show that the amplifier has a DC gain above 50 dB despite physical and environmental variations with a minimum gain bandwidth product of 540 MHZ and more than 55° phase margin. In addition, the simulated transient behaviour is shown to be robust, with a slew rate of 500 V/μs and a settling time of 7 ns with 1% accuracy for a C L of 0.3 pF.