Survey on memory management techniques in heterogeneous computing systems. Issue 2 (21st January 2020)

• Record Type: Journal Article
• Authors: Hazarika, Anakhi; Poddar, Soumyajit; Rahaman, Hafizur
• Is Part Of: IET computers & digital techniques. Volume 14:Issue 2(2020)
• Page Start: 47
• Page End: 60
• Publication Date: 2020-01-21
• Subjects: multiprocessing systems -- parallel processing -- cache storage -- computer architecture -- graphics processing units -- DRAM chips; large‐scale parallel computing -- off‐chip memory -- memory management unit -- data flow -- dynamic random access memory architecture -- memory‐centric hardware accelerator -- heterogeneous system -- processing‐in‐memory -- PIM systems -- memory access time -- self‐adaptive memory management schemes -- high‐speed processing scenario -- memory protection -- memory management techniques -- heterogeneous computing systems -- data scientists today -- processing infrastructure -- big data -- high‐performance computing workloads -- HPC workloads -- MMU controls -- resource management techniques -- DRAM architecture -- multiple graphics processing units -- CPU/GPU processes -- cache control; Computers -- Periodicals; Digital electronics -- Periodicals; Computer engineering -- Periodicals; Computer architecture -- Periodicals; Computer organization -- Periodicals; 621.39
• DOI: 10.1049/iet-cdt.2019.0092
• Languages: English
• ISSNs: 1751-8601

Abstract

Abstract : A major issue faced by data scientists today is how to scale up their processing infrastructure to meet the challenge of big data and high‐performance computing (HPC) workloads. With today's HPC domain, it is required to connect multiple graphics processing units (GPUs) to accomplish large‐scale parallel computing along with CPUs. Data movement between the processor and on‐chip or off‐chip memory creates a major bottleneck in overall system performance. The CPU/GPU processes all the data on a computer's memory and hence the speed of the data movement to/from memory and the size of the memory affect computer speed. During memory access by any processing element, the memory management unit (MMU) controls the data flow of the computer's main memory and impacts the system performance and power. Change in dynamic random access memory (DRAM) architecture, integration of memory‐centric hardware accelerator in the heterogeneous system and Processing‐in‐Memory (PIM) are the techniques adopted from all the available shared resource management techniques to maximise the system throughput. This survey study presents an analysis of various DRAM designs and their performances. The authors also focus on the architecture, functionality, and performance of different hardware accelerators and PIM systems to reduce memory access time. Some insights and potential directions toward enhancements to existing techniques are also discussed. The requirement of fast, reconfigurable, self‐adaptive memory management schemes in the high‐speed processing scenario motivates us to track the trend. An effective MMU handles memory protection, cache control and bus arbitration associated with the processors.