266–2133 MHz phase shifter using all‐digital delay‐locked loop and triangular‐modulated phase interpolator for LPDDR4X interface. Issue 12 (1st June 2017)

• Record Type: Journal Article
• Authors: Chae, J.‐H.; Kim, M.; Ko, H.; Jeong, Y.; Park, J.; Hong, G.‐M.; Jeong, D.‐K.; Kim, S.
• Is Part Of: Electronics letters. Volume 53:Issue 12(2017)
• Page Start: 766
• Page End: 768
• Publication Date: 2017-06-01
• Subjects: UHF phase shifters -- delay lock loops -- CMOS integrated circuits -- phase detectors -- delay lines; phase shifter -- LPDDR4X interface -- all‐digital delay‐locked loop -- triangular‐modulated phase interpolator -- jitter -- global DLL -- fast locking -- adaptive‐window phase detector -- folded delay line -- triangular‐modulated clock waveform -- CMOS process -- frequency 266 MHz to 2133 MHz -- size 65 nm; Electronics -- Periodicals; 621.381
• DOI: 10.1049/el.2017.1291
• Languages: English
• ISSNs: 0013-5194

Abstract

Abstract : A 266–2133 MHz phase shifter is proposed for LPDDR4X interface, utilising an all‐digital delay‐locked loop (DLL) and a triangular‐modulated phase interpolator (PI) to improve the jitter and linearity. The DLL consists of two kinds of DLLs: a global DLL to assist fast locking; and a local DLL which uses an adaptive‐window phase detector and a folded delay line to reduce jitter and improve linearity. The PI uses a triangular‐modulated clock waveform to achieve good linearity over a wide frequency range. The prototype chip is implemented in a 65 nm CMOS process. The measured jitter of the DLL is 3.08 psrms /19.93 pspp at 2133 MHz. The measured differential non‐linearity of the phase shifter is <0.91 LSB at 2133 MHz, and the power efficiency is about 2.7 mW/GHz.