3D device‐level simulation of charge separation from sidewall in vertical transfer gate pinned photodiode pixels for noise mitigation. Issue 5 (1st June 2020)

• Record Type: Journal Article
• Authors: Heidari, Sakineh; Alaibakhsh, Hamzeh; Azim Karami, Mohammad
• Is Part Of: IET circuits, devices & systems. Volume 14:Issue 5(2020)
• Page Start: 619
• Page End: 622
• Publication Date: 2020-06-01
• Subjects: photodiodes -- CMOS image sensors -- interference suppression -- ion implantation; charge separation -- vertical transfer gate pinned photodiode pixels -- noise mitigation -- vertical sidewall implantation -- noise reduction -- CMOS image sensor pixel -- interface traps -- photogenerated carriers -- floating diffusion region -- complete charge transfer -- signal-to-noise ratio -- 3D device-level simulation -- vertical transfer gate -- pixel output -- back-side-illuminated shared VTG pixel -- buried pinned photodiode -- equilibrium full-well capacity -- conversion gain -- pixel performance evaluation -- noise figure 37.0 dB -- distance 10.0 nm; Electronic circuits -- Periodicals; Electronic systems -- Periodicals; 621.381505
• DOI: 10.1049/iet-cds.2019.0501
• Languages: English
• ISSNs: 1751-858X

Abstract

Abstract : This study proposes vertical sidewall implantation for noise reduction of CMOS image sensor pixel employing a vertical transfer gate (VTG). The pixel performance is evaluated by 3D device‐level simulation. It is concluded that the proposed pixel's output is less sensitive to interface traps compared to similar previous work. In previous back‐side‐illuminated shared VTG pixel, which lacks the sidewall implantation for noise mitigation, photogenerated carriers were transferred to the floating diffusion (FD) region along with the interface. In the proposed pixel, the channel is separated from the interface, and photogenerated carriers are transferred with 10 nm distance from VTG. The proposed pixel has a complete charge transfer from the buried pinned photodiode to FD with 1274 e − /µm 2 equilibrium full‐well capacity. The conversion gain is 200 μV/e − and the signal‐to‐noise ratio is 37 dB.