A 32 GSps multiplexer with 1 kbit memory for arbitrary signal generation for testing digital‐to‐analogue converters. Issue 6 (1st November 2014)

• Record Type: Journal Article
• Authors: Khafaji, Mahdi; Carta, Corrado; Tittelbach‐Helmrich, Klaus; Micusik, Daniel; Fischer, Gunter; Scheytt, Johann Christoph; Ellinger, Frank
• Is Part Of: IET circuits, devices & systems. Volume 8:Issue 6(2014)
• Page Start: 459
• Page End: 468
• Publication Date: 2014-11-01
• Subjects: Ge-Si alloys -- digital-analogue conversion -- multiplexing equipment -- signal generators -- BiCMOS integrated circuits -- integrated circuit testing -- error statistics -- flip-flops -- clocks -- analogue-digital conversion -- driver circuits -- low-power electronics; multiplexer -- digital-to-analogue converter testing -- DAC testing -- bit-error rate tester -- built-in memory -- arbitrary test signal generator -- OFDM optical communication -- BiCMOS process -- power dissipation -- tree structure -- latch -- multiphase-clock architecture -- one-stage MUX architecture -- optimisation -- storage capacity 1 Kbit -- size 0.25 mum -- power 875 mW -- SiGe; Electronic circuits -- Periodicals; Electronic systems -- Periodicals; 621.381505
• DOI: 10.1049/iet-cds.2013.0333
• Languages: English
• ISSNs: 1751-858X

Abstract

Abstract : Recent high‐speed digital‐to‐analogue converters (DACs) cannot be easily characterised at their highest rate because of the very high cost of commercially available bit‐error rate testers at the required DACs rate. Among possible solutions, an inexpensive approach is the use of a multiplexer (MUX) with built‐in memory to provide the required bit stream for one input bit of the DAC. This work presents a half‐rate 32 GSps MUX with 1 kbit built‐in memory as a part of an arbitrary test signal generator for a DAC. The proposed system can be used to test DACs developed for future OFDM optical communications. Here, a bipolar‐CMOS (BiCMOS) 0.25 μm SiGe process is utilised. One challenge is to optimise the power dissipation of such an MUX which requires employing several techniques. At the system level, the conventional tree structure was avoided because of the high number of latches required to re‐time the clock and data signals. At the highest rates, a multiphase‐clock architecture was utilised which halves the number of latches compared with a tree structure. The phase margin of the multiphase‐clock structure is enhanced in this work. At lower rates, a one‐stage MUX architecture was used which also halves the number of latches. Additionally, the latency between the analogue–digital interface is discussed. All the implemented circuits including the biasing of the whole chip and its routing are presented. The design and optimisation of the clock driver for low‐power functionality is discussed. Measurement results show proper operation at 32 GSps. The total power dissipation is 875 mW, which is the lowest power among the designs usable for DAC testing and at the same rate class.