Column selection solutions for L1 data caches implemented using eight‐transistor cells. Issue 3 (1st May 2014)

• Record Type: Journal Article
• Authors: Farahani, Mostafa; Baniasadi, Amirali
• Is Part Of: IET computers & digital techniques. Volume 8:Issue 3(2014)
• Page Start: 118
• Page End: 128
• Publication Date: 2014-05-01
• Subjects: cache storage -- power aware computing -- SRAM chips; cache traffic overhead -- RB -- read bypassing -- buffering mechanism -- WG -- write grouping -- cache traffic reduction -- microarchitectural solutions -- cache access -- RMW -- read‐modify‐write operation -- cell stability -- 8T cells -- SRAM cells -- power dissipation -- voltage scaling -- eight‐transistor cells -- L1 data caches -- column selection solutions; Computers -- Periodicals; Digital electronics -- Periodicals; Computer engineering -- Periodicals; Computer architecture -- Periodicals; Computer organization -- Periodicals; 621.39
• DOI: 10.1049/iet-cdt.2013.0109
• Languages: English
• ISSNs: 1751-8601

Abstract

Abstract : Voltage scaling can reduce power dissipation significantly. SRAM cells (which are traditionally implemented by using six‐transistor cells) can limit voltage scaling because of stability concerns. Eight‐transistor (8T) cells were proposed to enhance cell stability under voltage scaling. 8T cells, however, suffer from costly write operations caused by the column selection issue. A proposed technique, Read‐Modify‐Write (RMW), addresses this issue at the expense of extra read operations. The extra cache access affects performance and power dissipation negatively. In this study, the authors show that a large share of the cache accesses in RMW is unnecessary. To address this inefficiency, they propose two micro‐architectural solutions with the aim of reducing the overhead imposed by RMW. The authors first proposed technique, Write Grouping (WG), relies on a buffering mechanism that identifies the redundant and the unnecessary cache accesses imposed by RMW and eliminates them. Their second technique, WG and Read Bypassing (WG + RB), improves the WG's efficiency further at a negligible area cost. Their simulation results show that on average, WG and WG + RB reduce RMW's cache traffic overhead by 15% and 20%, respectively. They show that WG and WG + RB also improve average performance by 30% and 37%, respectively.