Protecting IP core during architectural synthesis using HLT‐based obfuscation. Issue 13 (1st June 2017)

• Record Type: Journal Article
• Authors: Sengupta, A.; Roy, D.
• Is Part Of: Electronics letters. Volume 53:Issue 13(2017)
• Page Start: 849
• Page End: 851
• Publication Date: 2017-06-01
• Subjects: logic circuits -- microprocessor chips -- logic design -- program compilers -- program processors -- particle swarm optimisation -- circuit optimisation; IP core protection -- architectural synthesis -- HLT‐based obfuscation -- intellectual property core -- reverse engineering -- structural obfuscation methodology -- multiple compiler‐based high‐level transformations -- functionally equivalent designs -- HLT techniques -- redundant operation elimination -- logic transformation -- tree height transformation -- area‐delay tradeoff -- low‐cost obfuscated design -- particle swarm optimisation‐based exploration framework -- low‐cost obfuscated IP designs; Electronics -- Periodicals; 621.381
• DOI: 10.1049/el.2017.1329
• Languages: English
• ISSNs: 0013-5194

Abstract

Abstract : For protecting an intellectual property (IP) core, it must be harder to reverse engineer. Structural obfuscation can play an important role in achieving this goal. A novel structural obfuscation methodology during architectural synthesis using multiple compiler‐based high‐level transformations (HLTs) that yield functionally equivalent designs (data flow graphs) which are camouflaged in identity is proposed. The proposed obfuscation methodology is driven through a number of HLT techniques such as redundant operation elimination, logic transformation and tree height transformation. In addition to performing obfuscation, performing area–delay tradeoff during exploring low‐cost obfuscated design is also possible using these HLT techniques in the proposed methodology. Owing to multiple stages of HLT incorporated in the proposed approach during obfuscation, it yields a highly robust design which on integration with particle swarm optimisation‐based exploration framework produced low‐cost obfuscated IP designs. Results of the proposed approach yielded an enhancement in strength of obfuscation of 20.19% and reduction in obfuscated design cost of 59.66% compared with a similar approach.