Low‐cost security aware HLS methodology. Issue 2 (10th January 2017)
- Record Type:
- Journal Article
- Title:
- Low‐cost security aware HLS methodology. Issue 2 (10th January 2017)
- Main Title:
- Low‐cost security aware HLS methodology
- Authors:
- Sengupta, Anirban
Bhadauria, Saumya
Mohanty, Saraju P. - Abstract:
- Abstract : Owing to massive complexity of modern digital integrated circuits (ICs) disabling complete in‐house development, globalisation of the design process establishes itself as an inevitable solution for faster and efficient design. However, globalisation incurs importing intellectual property (IP) cores from various third party vendors, rendering an IP susceptible to hardware threats. To provide trust and security in digital ICs within user constraints, design of a low‐cost optimised dual modular redundant, through Trojan secured high‐level synthesis (HLS) methodology, is crucial. This study presents exploration of a low‐cost optimised HLS solution capable of handling hardware Trojan (providing security) that alters computational output. The key contributions of the study are as: (i) novel low‐cost security‐aware HLS approach; (ii) novel encoding for representing bacterium in the design space (comprising of candidate datapath resource configuration and vendor allocation information for Trojan secured solution); and (iii) novel exploration process of an efficient vendor allocation procedure that assists in yielding a low‐cost Trojan secured schedule. Experimental results indicate significant reduction in the cost of security‐aware HLS solution (82.4%) through the proposed approach compared with a recent approach.
- Is Part Of:
- IET computers & digital techniques. Volume 11:Issue 2(2017)
- Journal:
- IET computers & digital techniques
- Issue:
- Volume 11:Issue 2(2017)
- Issue Display:
- Volume 11, Issue 2 (2017)
- Year:
- 2017
- Volume:
- 11
- Issue:
- 2
- Issue Sort Value:
- 2017-0011-0002-0000
- Page Start:
- 68
- Page End:
- 79
- Publication Date:
- 2017-01-10
- Subjects:
- high level synthesis -- invasive software -- integrated circuit design -- encoding -- industrial property -- resource allocation -- scheduling
low‐cost security aware HLS methodology -- digital integrated circuits -- IC -- design process globalisation -- intellectual property cores -- IP cores -- third party vendors -- hardware threats -- user constraints -- low‐cost optimised dual modular redundant design -- Trojan secured high‐level synthesis methodology -- low‐cost security‐aware HLS approach -- encoding -- design space -- candidate datapath resource configuration -- vendor allocation information -- vendor allocation procedure exploration process -- low‐cost Trojan secured schedule
Computers -- Periodicals
Digital electronics -- Periodicals
Computer engineering -- Periodicals
Computer architecture -- Periodicals
Computer organization -- Periodicals
621.39 - Journal URLs:
- http://digital-library.theiet.org/content/journals/iet-cdt ↗
http://ieeexplore.ieee.org/servlet/opac?punumber=4117424 ↗
http://www.ietdl.org/IET-CDT ↗
https://ietresearch.onlinelibrary.wiley.com/journal/1751861x ↗
http://www.theiet.org/ ↗ - DOI:
- 10.1049/iet-cdt.2016.0014 ↗
- Languages:
- English
- ISSNs:
- 1751-8601
- Deposit Type:
- Legaldeposit
- View Content:
- Available online (eLD content is only available in our Reading Rooms) ↗
- Physical Locations:
- British Library DSC - 4363.252300
British Library DSC - BLDSS-3PM
British Library HMNTS - ELD Digital store - Ingest File:
- 17381.xml