A High‐linearity Input‐Buffer with high output common‐mode stability for 10bit 3.2GSs ADC. Issue 13 (1st June 2020) - Sun, Ting; Li, Jing; Ning, Ning; Wu, Kejun; Yu, Qi
Abstract : A high‐linearity input‐buffer with high output common‐mode stability for 10‐bit 3.2 GS/s ADC is proposed in this Letter. The buffer is mainly composed of a source follower for strong driving ability. To enhance its linearity, a feed forward signal path from input to output is proposed. A replica buffer‐based common‐mode feedback is designed to achieve high output common‐mode stabilisation of input‐buffer. The prototype is implemented in 40 nm CMOS process. The output common‐mode variation is reduced from 200 to 1 mV. Input‐buffer consumes 96 mW in 3.2 GHz sampling rate and achieves 69.3 dB spur‐free dynamic range at 1581 MHz input frequency.