Soft error rate estimation of combinational circuits based on vulnerability analysis. Issue 6 (1st November 2015)

• Record Type: Journal Article
• Authors: Raji, Mohsen; Pedram, Hossein; Ghavami, Behnam
• Is Part Of: IET computers & digital techniques. Volume 9:Issue 6(2015)
• Page Start: 311
• Page End: 320
• Publication Date: 2015-11-01
• Subjects: integrated circuits; soft error rate estimation -- combinational circuits -- vulnerability analysis -- nanometer integrated circuits -- SER estimation -- probabilistic vulnerability window -- PVW -- single event transient -- SET -- observable errors -- computational framework -- circuit gates -- backward‐traversing algorithm -- circuit designers -- SER estimation methods -- Monte Carlo -- fault injection simulation -- ISCAS'85 benchmark circuits; Computers -- Periodicals; Digital electronics -- Periodicals; Computer engineering -- Periodicals; Computer architecture -- Periodicals; Computer organization -- Periodicals; 621.39
• DOI: 10.1049/iet-cdt.2014.0157
• Languages: English
• ISSNs: 1751-8601

Abstract

Abstract : Nanometer integrated circuits are getting increasingly vulnerable to soft errors and making the soft error rate (SER) estimation an important challenge. In this study, a novel approach is proposed for SER estimation of combinational circuits based on vulnerability analysis. The authors introduce a concept called probabilistic vulnerability window (PVW) which is an inference of necessary conditions for a single event transient (SET) to cause observable errors in the circuit. A proposed computational framework calculates PVWs for all circuit gates in a backward‐traversing algorithm enabling the circuit designers for an accurate and efficient SER estimation. Experimental results show that the proposed approach is 2× faster than the traditional SER estimation methods and keep its efficiency when it is applied for estimating the SER considering various different SET widths while runtime of traditional estimation methods increases in such cases. In addition, results verify the accuracy (average difference of 0.02) and speedup (about four orders of magnitude) of the proposed method when compared with the Monte Carlo‐based fault injection simulation on ISCAS'85 benchmark circuits.