Design optimisation of multiplier‐free parallel pipelined FFT on field programmable gate array. Issue 7 (22nd October 2020)

• Record Type: Journal Article
• Authors: Godi, Prasanna Kumar; Krishna, Battula Tirumala; Kotipalli, Pushpa
• Is Part Of: IET circuits, devices & systems. Volume 14:Issue 7(2020)
• Page Start: 995
• Page End: 1000
• Publication Date: 2020-10-22
• Subjects: discrete Fourier transforms -- hardware description languages -- pipeline processing -- digital signal processing chips -- fast Fourier transforms -- field programmable gate arrays -- mathematics computing; design optimisation -- multiplier‐free parallel -- field programmable gate array -- frequency domain -- time domain -- digital signal -- image processing -- general filtering -- spread‐spectrum communications -- FFT operations -- radix‐2 decimation -- frequency method -- efficient FFT architecture -- FFT stores -- R2DIF method -- complex twiddle factors -- uniform Montgomery algorithm -- shift‐add method -- multiplication process -- FFT implementation; Electronic circuits -- Periodicals; Electronic systems -- Periodicals; 621.381505
• DOI: 10.1049/iet-cds.2019.0512
• Languages: English
• ISSNs: 1751-858X

Abstract

Abstract : Fast Fourier transform (FFT) is utilised to minimise the complexity of discrete Fourier transform by converting signals from frequency domain to time domain and conversely. Digital signal processing systems like image processing, general filtering, sonar, spread‐spectrum communications and convolutions use this FFT operations. Radix‐2 decimation in frequency (R2DIF) method is designed to execute an efficient FFT architecture in this study. Each and every state of the FFT stores the input and output the data using the R2DIF method. Also, the complex twiddle factors in FFT are replaced by the proposed uniform Montgomery algorithm. This technique simply performs the shift‐add method instead of the multiplication process which also enhances the convergence of the calculation. So, the FFT implementation is done with the help of the proposed method which reduces the usage of chips in the process. Based on this approach, it performs the operation of FFT from 16 points to 1024 points and the performance of this proposed method is compared with existing approaches. Moreover, it does not require expensive dedicated functional blocks and uses only distributed logic resources. The simulation is carried out by the Xilinx platform using Verilog coding. The proposed design outperforms conventional methods in terms of less usage power and high speed.