MFSFET two‐bit 1T1C DRAM memory design and empirical data. Issue 6 (1st March 2016) - Hunt, M.R.; Mitchell, C.; McCartney, C.L.; Ho, F.D.
Abstract : Operation of the 1‐transistor, 1‐capacitor dynamic random access memory cell that allows for two‐bit operation, double the typical storage capacity, is explored. By using a metal‐ferroelectric‐semiconductor field‐effect transistor, a second bit is captured in the ferroelectric layer polarisation resulting from negative and positive polarisation states. As a result, new modes of operation are created giving non‐volatile, long‐term storage as well as decreased power consumption and radiation hardening. A typical write and read operating cycle is outlined in‐depth and used to verify operation indicating four distinct states representing the two bits. The resulting empirical data gives a comprehensive presentation of the read cycle of the memory cell. Methods for determining the polarisation state of the transistor are also explored and used to determine the average value for measured channel resistance using three types of transistors, each having different channel width and length.