Single‐configuration fault detection in application‐dependent testing of field programmable gate array interconnects. Issue 3 (1st May 2013)

• Record Type: Journal Article
• Authors: Nandha Kumar, Thulasiraman; Almurib, Haider Abbas F.; Lombardi, Fabrizio
• Is Part Of: IET computers & digital techniques. Volume 7:Issue 3(2013)
• Page Start: 132
• Page End: 141
• Publication Date: 2013-05-01
• Subjects: computational complexity -- fault diagnosis -- field programmable gate arrays -- logic testing -- table lookup; polynomial time complexity -- Xilinx Virtex5 -- Xilinx Virtex4 -- walking‐1 test set -- bridging faults -- stuck‐at faults -- 1‐BSF -- 1‐bit sum function -- primary input‐outputs -- interconnect configuration -- logic deactivation -- logic activation -- LUT programming function -- look up tables -- FPGA interconnects -- field programmable gate array interconnects -- application‐dependent testing -- single‐configuration fault detection; Computers -- Periodicals; Digital electronics -- Periodicals; Computer engineering -- Periodicals; Computer architecture -- Periodicals; Computer organization -- Periodicals; 621.39
• DOI: 10.1049/iet-cdt.2012.0117
• Languages: English
• ISSNs: 1751-8601

Abstract

Abstract : This study presents a new method for application testing of field programmable gate array (FPGA) interconnects at run time. This method utilises new features related to the function for the programming of the look up tables (LUTs), the utilisation (by logic activation/deactivation) of the nets in a interconnect configuration as well as the primary (unused) input/outputs (IOs) of the FPGAs. A new LUT programming function is introduced; the proposed method retains the original interconnect configuration and modifies the function of the LUTs using the so‐called 1‐bit sum function (1‐BSF); the 1‐BSF detects all possible stuck‐at and bridging faults (of all cardinalities) by utilising the all zeros' vector and a walking‐1 test set. As validated by simulation for benchmark circuits (implemented on the Xilinx Virtex4 and Virtex5), the proposed method (with a polynomial time complexity) results in a single test configuration with 100% coverage. These results also show that the proposed method requires a larger number of test vectors and an availability of unused IOs.