Impact of spintronic memory on multicore cache hierarchy design. Issue 2 (25th January 2017)

• Record Type: Journal Article
• Authors: Ma, Cong; Tuohy, William; Lilja, David J.
• Is Part Of: IET computers & digital techniques. Volume 11:Issue 2(2017)
• Page Start: 51
• Page End: 59
• Publication Date: 2017-01-25
• Subjects: cache storage -- multiprocessing systems -- MRAM devices; spintronic memory -- multicore cache hierarchy design -- spin‐transfer torque‐magnetic random access memory -- STT‐MRAM -- energy consumption -- multicore processor -- PARSEC -- Splash2; Computers -- Periodicals; Digital electronics -- Periodicals; Computer engineering -- Periodicals; Computer architecture -- Periodicals; Computer organization -- Periodicals; 621.39
• DOI: 10.1049/iet-cdt.2015.0190
• Languages: English
• ISSNs: 1751-8601

Abstract

Abstract : Spintronic memory [spin‐transfer torque‐magnetic random access memory (STT‐MRAM)] is an attractive alternative technology to CMOS since it offers higher density and virtually no leakage current. Spintronic memory continues to require higher write energy, however, presenting a challenge to memory hierarchy design when energy consumption is a concern. This study motivates the use of STT‐MRAM for the first‐level caches of a multicore processor to reduce energy consumption without significantly degrading the performance. The large STT‐MRAM first‐level cache implementation saves leakage power. Moreover, the use of small level‐0 cache regains the performance drop due to STT‐MRAM long write latencies. The combination of both reduces the energy‐delay product by 65% on average compared with CMOS baseline. The proposed STT hierarchy also shows good scalability over the CMOS with a few benchmarks which scale significantly better. The PARSEC and Splash2 benchmark suites are analysed running on a modern multicore platform, comparing performance, energy consumption and scalability of the spintronic cache system to a CMOS design.