Impact of PZT gate‐stack induced negative capacitance on analogue/RF figures‐of‐merits of electrostatically‐doped ferroelectric Schottky‐barrier tunnel FET. Issue 4 (28th May 2019)

• Record Type: Journal Article
• Authors: Singh, Sangeeta; Sinha, Ruchir; Kondekar, Pravin Neminath
• Is Part Of: IET circuits, devices & systems. Volume 13:Issue 4(2019)
• Page Start: 435
• Page End: 441
• Publication Date: 2019-05-28
• Subjects: surface potential -- semiconductor device models -- semiconductor doping -- Schottky gate field effect transistors -- ferroelectric devices -- lead compounds -- tunnel transistors -- Schottky barriers -- leakage currents; dopant-free technique -- charge plasma Schottky-barrier tunnel FET -- ED-FE-TFET -- ED-FE-SBTFET -- PZT gate-stack induced negative capacitance -- electrostatically-doped ferroelectric Schottky-barrier tunnel FET -- dopant-free technology -- negative capacitance behaviour -- intrinsic amplifier -- applied gate bias -- gate controllability -- switching transitions -- ferroelectric Schottky-barrier tunnel field-effect transistor -- high frequency FOM -- radio-frequency figures-of-merit -- analogue figures-of-merit -- lead zirconium titanate gate stack -- PZT gate stack -- electric dipoles -- surface potential -- ambipolar current -- ion implantation -- thermal annealing -- thermal budget -- digital circuits -- PZT; Electronic circuits -- Periodicals; Electronic systems -- Periodicals; 621.381505
• DOI: 10.1049/iet-cds.2018.5276
• Languages: English
• ISSNs: 1751-858X

Abstract

Abstract : In this work, the authors investigate analogue and radio‐frequency (RF) figures‐of‐merit (FOM) of electrostatically‐doped ferroelectric Schottky‐barrier tunnel field‐effect transistor (FET) (ED‐FE‐SBTFET) by deploying PZT (lead zirconium titanate) gate stack and dopant‐free technology. This PZT gate stack results in negative capacitance behaviour as a result of the positive feedback among the electric dipoles within it. It realises an intrinsic amplifier to amplify the surface potential due to the applied gate bias and enhances the gate controllability significantly. As a result it facilitates lower ambipolar current, considerably high drive current and faster switching transitions. As the structure is realised by using dopant‐free technique it ensures simplified fabrication process as it avoids the need of ion implantation and thermal annealing, reduces thermal budget. Here, a detailed comparison is carried‐out between charge plasma Schottky‐barrier tunnel FET and ED‐FE‐TFET for their high frequency FOMs such as cut‐off frequency ( f T ), gain bandwidth product, transconductance generation factor and so on. The higher I ON / I OFF ratio of ED‐FE‐SBTFET reduces the static and dynamic both types of powers in digital circuits, while higher g m / I D ratio ensures lower bias power of an amplifier.