LDPC check node implementation using reversible logic. Issue 4 (30th May 2019)

• Record Type: Journal Article
• Authors: Awais, Muhammad; Razzaq, Anas; Ahmed, Ashfaq; Masera, Guido
• Is Part Of: IET circuits, devices & systems. Volume 13:Issue 4(2019)
• Page Start: 443
• Page End: 455
• Publication Date: 2019-05-30
• Subjects: transistors -- parity check codes -- decoding -- forward error correction -- CMOS integrated circuits -- logic gates -- low-power electronics -- logic circuits -- logic design; LDPC check node implementation -- low energy dissipation -- information-lossless nature -- practical complexity applications -- low density parity check decoding -- forward error correction domain -- LDPC decoding -- check node processor -- decoding algorithm -- low-power LDPC CN architecture -- reversible logic gates -- transistor level design -- reversible blocks -- CN functionality -- schematic checks -- power delay product -- complementary metal–oxide–semiconductor technology -- postlayout simulations -- digital design paradigm -- postlayout area; Electronic circuits -- Periodicals; Electronic systems -- Periodicals; 621.381505
• DOI: 10.1049/iet-cds.2018.5222
• Languages: English
• ISSNs: 1751-858X

Abstract

Abstract : Reversible logic is an emerging digital design paradigm which promises low energy dissipation; thanks to its information‐lossless nature. True potential of this exciting concept can only be assessed by facing the design of practical complexity applications. Low density parity check (LDPC) decoding is one such application from forward error correction domain. The core of LDPC decoding is the check node (CN) processor, which executes the decoding algorithm and constitutes a major portion of decoder's overall power consumption. This work proposes a low‐power LDPC CN architecture using reversible logic gates. Transistor level design and full custom layout of proposed architecture is carried out on UMC 90 nm complementary metal–oxide–semiconductor technology. All reversible blocks of proposed CN are optimised for quantum cost, garbage outputs and transistor count. The CN functionality is validated with post‐layout simulations, layout versus schematic checks and design rule checks. The proposed CN occupies a post‐layout area of 0.013 mm 2, achieves up to 4.3 GHz frequency and consumes 52 μ W power. The performance of proposed CN is also compared with its implementation using irreversible gates. The proposed CN achieves about 300% reduction in power delay product with affordable complexity as compared to its classical implementation.