1.1‐V, 8‐bit, 12 MS/s asynchronous reference‐free successive‐approximation‐register analogue‐to‐digital converter in 0.18 μm CMOS with separated capacitor arrays. Issue 1 (1st January 2013)

• Record Type: Journal Article
• Authors: Huang, Guanzhong; Lin, Pingfen
• Is Part Of: IET circuits, devices & systems. Volume 7:Issue 1(2013)
• Page Start: 1
• Page End: 8
• Publication Date: 2013-01-01
• Subjects: analogue-digital conversion -- capacitors -- CMOS integrated circuits; asynchronous reference free successive approximation register -- capacitor arrays -- charge recycling method -- power consumption -- MATLAB simulation -- energy reduction -- helper array -- aggressive unit capacitance layout -- capacitor layout distribution -- geometric shape -- wiring parasitics -- oversampled system clock -- asynchronous timing control -- reference free configuration -- power supply -- buffered voltage references -- CMOS process -- analogue to digital converter -- voltage 1.1 V -- size 0.18 mum -- power 130 muW; Electronic circuits -- Periodicals; Electronic systems -- Periodicals; 621.381505
• DOI: 10.1049/iet-cds.2012.0253
• Languages: English
• ISSNs: 1751-858X

Abstract

Abstract : This study presents an 8‐bit asynchronous reference‐free successive‐approximation‐register analogue‐to‐digital converter (ADC). A novel charge recycling method is proposed to decrease the power consumption by switching the two separated capacitor arrays alternatively in the first four phases of one conversion. The last four phases stick to the conventional method. According to the calculation and the MATLAB simulation, 67% energy reduction is obtained. The four largest capacitors in the main array and the two capacitors in the helper array are broken into halves to generate the positive and negative comparison references, respectively. Combining an aggressive unit capacitance layout scheme and the proposed capacitor layout distribution, the matching performance, the geometric shape and the wiring parasitics are improved. The over‐sampled system clock is not required with the asynchronous timing control of the successive comparisons. The reference‐free configuration utilises power supply and ground instead of two dedicated buffered voltage references. The prototype ADC is fabricated in semiconductor manufacturing international corporation (SMIC) 0.18 μm complementary metal oxide semiconductor (CMOS) process. At 12 MS/s sampling rate and 1.1 V power supply, it consumes 130 μW and achieves a signal‐to‐noise‐and‐distortion‐ratio of 47.4 dB, resulting in a figure‐of‐merit of 58.4 fJ/conversion‐step and an active area of 0.1 mm 2 .